1. Field of the Invention
The present invention relates to a power on reset pulse generating circuit for initializing a semiconductor integrated circuit when turning the power on.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a conventional power on reset pulse generating circuit shown in, for example, Japanese Patent Laying-Open Gazette No. 250715/1985. Referring to FIG. 1, numeral 1 denotes a MOS transistor having its drain connected to a node N1, its gate connected to a supply terminal supplying the voltage V.sub.CC and its source connected to the ground GND; numeral 2 denotes an inverter having its input connected to the node N1; numeral 3 denotes a waveform shaping circuit (in this example, being formed of two inverters) having its input connected to the output of the inverter 2 and its output connected to a node N2; numeral 4 denotes a MOS transistor having its drain connected to the node N1, its gate connected to the node N2 and its source connected to the ground GND; numeral 5 denotes an inverter having its input connected to the node N2 and outputting a power on reset pulse a to an output terminal T3; numeral 6 denotes a capacitor having one end connected to a supply terminal supplying the voltage V.sub.CC and the other end connected to the node N1.
The operation of the circuit will be hereinafter described with reference to FIG. 2 showing the voltage waveform at each portion. As shown in FIG. 2, before turning the power on, V.sub.CC =0 V ((a) in FIG. 2)) and each node is discharged to 0 V ((b) and (c) in FIG. 2). When the power is turned on at time t0, the potential of the node N1 rises to approximately the supply voltage due to the coupling of the capacitor 6, as shown as (b) in FIG. 2 and then it falls according to the time constant defined by the capacitance of the capacitor 6 and the on resistance of the transistor 1. While the potential of the node N1 is higher than the logical threshold value V.sub.TH2 of the inverter 2, the node N2 is at the "L" level, the MOS transistor 4 is off and the output terminal T3 is at the "H" level, as shown as (c) in FIG. 2. When the potential of the node N1 becomes lower than V.sub.TH2 at time t1, the node N2 becomes "H" level, the MOS transistor 4 turns on discharging the node N1 to 0 V and, simultaneously, the output terminal T3 becomes "L" level.
As described above, using the circuit of FIG. 1, a power on reset pulse a ((d) in FIG. 2) having the pulse width determined by the capacitance of the capacitor 6 and the on resistance of the MOS transistor 1 can be generated after turning the power on.
In the conventional power on reset pulse generating circuit structured as above, a sufficient level of the power on reset pulse a can not be obtained in case where the supply voltage rises very slowly, as shown by the waveform in FIG. 3. This problem will be described with reference to FIG. 3.
If the supply voltage V.sub.CC rises slowly from the time t2 (as (a) in FIG. 3), the node N1 also rises slowly corresponding to the supply voltage V.sub.CC (as (b) in FIG. 3). If the time constant of the supply voltage rise is larger than the above described time constant defining the pulse width of the power on reset pulse, the potential of the node N1 begins to fall from the time when V.sub.CC exceeds the threshold value V.sub.TH1 of the MOS transistor 1 and it becomes lower than the logical threshold value V.sub.TH2 of the inverter 2 at the time t3, where the node N2 becomes "H" level (as (c) in FIG. 3), and the potential of the node N1 is discharged to 0 V. On this occasion, the reset pulse a as (d) in FIG. 3 is held at the "H" level until the time t3. However, if V.sub.CC does not sufficiently rise at the time t3, the "H" level of the reset pulse a is low since the "H" level potential of the reset pulse a is approximately the same as the supply voltage, with the result of a possibility that a pulse necessary for initializing other circuits cannot be obtained.
Another prior art, U.S. Ser. No. 571,028 now U.S. Pat. No. 4,591,745 entitled "Power On Reset Pulse Generating Device", filed on Jan. 16th, 1984 discloses a circuit for generating a reset pulse formed on a chip of a CMOS integrated circuit which can be manufactured according to a conventional manner.